SUMMARY
Experienced Design For Testability (DFT) engineer, specializing in ATPG using Mentor Graphics TestKompress and FastScan tools, and with ATPG DFT modeling.
Knows VCS, Verilog, Verdi tools.
Write many Perl and shell scripts to facilitate work.
EXPERIENCE
Intel, Austin, Texas
DFX Engineer 2013-2015
o Processor Test Pattern Generation using TestKompress
Enhanced and Maintained ATPG and Pattern Verification flows
Netlogic Microsystems/Broadcom, Santa Clara, California
Contract/Principal DFT Engineer 2011-2013
o Memory ATPG Modeling
Block and chip Test Pattern Generation using TestKompress
Avago Technologies, Fort Collins, Colorado
Contract Design For Test Engineer 2011
o TestKompress/FastScan Test Pattern Generation for Memories
Created Path Delay and Transition Patterns for three chips
Mentor Graphics, Wilsonville, Oregon
Corporate Applications Engineer, Customer Support Division 2007-2010
o Customer Support for DFT, ATPG, DRC, Yield Analysis tools
TestKompress/FastScan DRCs and ATPG; Pattern Diagnosis
Advanced Micro Devices, Austin, Texas
Contract Design For Test Engineer 2006-2007
Generated and verified DFT models for microprocessors.
Executed DRC and ATPG of cells, RLMs, and chip.
Generated and verified test patterns for chip.
FastScan Test Pattern generation and Design Rule Checks
Freescale/Mot...
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