Profile
Technology Development and Semiconductor (Product / Yield Management) Professional with 6 years of extensive experience in the Process Development, Product, Testing and Yield Control of semiconductor products:
2 years of start-up business development and program management experience as business partner and manager with outstanding team leadership and communications skills. Principle decision maker in business strategy execution, marketing, revenue generation/cost control and recruitment.
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Engineering/Technical Qualifications
+ Yield Improvement Strategy Development
+ Process Reengineering/Integration
+ Design of Experiments (DOE)
+ Failure Mode and Effect Analysis (FMEA)
+ Wafer Testing and Sorting
+ Component Specification Development
+ Six Sigma Green Belt
+ Process Flow Mapping
+ Process Capability Analysis
+ Design of SPC Metrics and Feedback Mechanism
+ Optical Engineering: Photometric/Colorimetric Analysis
+ LED Packaging
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Work Experience
[ Product Engineer ]
Bridgelux LED
- Livermore, CA (09/2012-02/2013)
+ Key player in New Product Introduction (NPI) Product and Testing Group
+ Monitors yield abnormalities and analyzes test photometric data through performance reports and initiates investigation on efficacy and process aberration
+ Manages Global Data Correlation and data systems with Contract Manufacturers in Taiwan, PRC and Malaysia
+ Collaborates with Marketing and Sales Department to determine Datasheets/Specifications for packaged LED products
[ Foundry Process Integration Engineer ]
Telefunken Semiconductor America
- Roseville, CA (12/2011-09/2012)
+ Principle developer of the 0.25um High Voltage (12V/24V/36V/80V) Bipolar-CMOS-DMOS (BCDMOS) Power Device process development.
+ Successfully reengineered the existing 0.25um logic process to be fully foundry compatible (FCT); performed Design of Experiments (DOE) on transistor parameter tuning (Channel Length, VT, IDsat, BV, etc) to meet industry specs
+ Integrated the revamped process with a third-party module to generate full HV BiCDMOS flow
+ Researches and develops device structures (e.g., Doubly-Masked Deep Trench Isolation, 8um Backside Contacts [patents pending], etc) and new devices (e.g., UTM Ultra Thick Metal, Zener diode, Schottky diode, MIM capacitors) to adapt to smart-power, high voltage specifications
+ Interfaced with process simulation engineer and device layout engineer to develop test chip and optimize Process Control Monitoring (PCM) dimensions
[ Process Engineer, In-Line Yield Management ]
NEC Electronics/Renesas Electronics America
- Roseville, CA (02/2007-12/2011)
+ Engineer-in-chief for yield improvement on NOR Flash module: comprehensive knowledge in processes of Flash macro formation; familiarity with metrology technologies that include defect detection, critical dimension (CD), electrical parameter map and sorting
+ Devise strategic process and failure reaction specs that balance excursion cost and Turn Around Time (TAT) for an organization of 600+ employees; standardized specification methodologies by employing mathematical models such as Negative Binomial. Develop component specifications based on failure analysis and communicate requirements to internal and external customers. Conduct defect trend analyses, develop repeatable data workflows using VBA/Klarity® (centralized defect database)
+ Responsible for setting milestones to qualify new metrology and automatic testing equipments (ATE), and develop Standard Operating Procedures (SOP) to ensure the lowest Mean Time Between Failures
+ Familiarity with established manufacturing protocols & methodologies: 5S, Zero-Defect, Lean Manufacturing, Six Sigma, SPC, QMS, ISO9001, Process Capability calculations (Cp/Cpk)
>> Results: Startup product line yield improved from 30% to > 75% through defect reduction and maintained long term product yield at >98%
[ General Manager and Partner ]
Ahead Education Corporation
- San Francisco, CA (04/2005-01/2007)
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