Texas Instruments Inc (TI), 1995 – 2012:
Semi-conductor 20nm Development Process Integration Manager, 2011 – 2012:
I was responsible for the TI 20nm (C20.M) process technology node development. I managed the team which developed the spice models, component specifications, process flow integration, process control and design layout rule parts of the Process Design Kit (PDK) up to early release for design, v0.5. After C20.M development was halted in 2nd quarter of 2012, I performed comparisons across 28/20/16/14 nm, internal and external, process technology nodes.
Semi-conductor 45nm Development Process Integration Manager, 2009 – 2010:
My team completed the process development, qualification and ramp of the 45 nm (TI C014.M) technology node across several foundry partners. This involved improving transistor performance, yield and SoC component development which culminated in v2.0 (mature production) PDK release.
Semi-conductor Project Manager, 2007 – 2009:
I managed two parallel process technology startups, C021.A and D021.A embedded DRAM, using TI process technology and produced in the TSMC foundry. In this role, I coordinated activities across all facets of the semiconductor design, process development and production qualification.
Semi-conductor Fabrication Product Engineer, 1998 – 2007:
I was directly responsible for the yield ramp on new process technologies (C035.1/.B – 120 nm, C021.M/.A – 65 nm) across multiple factories both internal and external to Texas Instruments. In this role, I was responsible for enabling the test, characterization and performance improvement across several SoC designs manufactured by TI. I have direct experience with high volume manufacturing and leading edge technology development. My areas of expertise are embedded SRAM yield, physical/electrical fuse programmation and speed/leakage optimization. In 2003, I was awarded the TI Senior Member of Technical Staff title.
Thin Film Module Equipment Engineering (EE) Manager, 1995 – 1998:
I managed up to 8 engineers and 32 technicians across a 24 hours/day, 7-days/week operations. I was directly responsible for $1 Million/month maintenance budget, $100 Million in equipment purchase decisions and equipment performance improvement activities in addition to the administration responsibilities of a front line manager. I actively recruited engineers and technicians to grow the DMOS5 fab EE group from 30 to over 100 members.
Intel Corporation, 1993-1995:
Process/Equipment Installation Engineer:
I installed, characterized and released the equipment/process to manufacturing for the semi-conductor equipment in the Thin Film module which included RTP, PVD, PECVD, WCVD and APCVD. I developed do...
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