Mark J. Cianchetti
Education
6/06 – 9/11
MS/PhD, Electrical and Computer Engineering, Cornell University, GPA 3.8/4.0
Minor field, Computer Science
8/02 – 5/06
Bachelor of Science, Electrical Engineering, University at Buffalo, GPA 4.0/4.0
8/02 – 5/06
Bachelor of Science, Computer Engineering, University at Buffalo, GPA 4.0/4.0
Professional Experience
Computer Architect, Oct. 2011 – Present, Intel Corporation, Power Architecture Group
Knights Landing (KNL) High Performance Computing (Xeon Phi), product development
* Responsibilities include understanding the microarchitecture of firmware-implemented power management features and driving/validating changes for KNL.
Research Assistant, June 2006 – Sept. 2011, Cornell University, Computer Systems Laboratory
* Dissertation: On-Chip Interconnect for Future Microprocessors (Aug. 2007 – Sept. 2011)
* Multicore reconfigurable architectures (Jan. 2007 – Aug. 2007)
* Application scheduling for unreliable multicore architectures (June 2006 – Dec. 2006)
Teaching Assistant, Cornell University
* ECE 475 Computer Architecture (Fall 2006, Fall 2008)
* ECE 230 Principles of Digital Logic Design (Spring 2007)
Research Assistant, Jan. 2003 – Dec. 2005, University at Buffalo, Ctr. For Computational Research
* DNA sequence alignment algorithm analysis and design
Research Assistant, Summer 2005, University at Buffalo, Laboratory for Spectroscopic Evaluation
* Fabrication and design of novel single electron devices
Related Courses
Graduate Coursework
* Advanced Computer Architecture
* Digital VLSI Design
* Parallel Computer Architecture
* Heuristic Methods for Optimization
* Artificial Intelligence
* Fiber and Integrated Optics
* Memory Systems
* Interconnection Networks
Undergraduate Coursework
* Operating Systems
* Software Engineering I & II
* Computer Organization
* Microprocessor Design & Lab
* Computer Architecture
* Electronic Devices & Circuits
* Digital Principles
* Signal Analysis and Transform
Honors
* Intel Knights in Shining Armor Award, 2012
* Intel Recognition Awards (5/12, 8/12, 9/12, 10/12)
* Intel Graduate Research Fellowship, 2009-2010
* Best Paper Award nomination (FPL’08)
* National Science Foundation Graduate Research Fellowship Honorable Mention, 2008
* National Grid Graduate Research Fellowship, 2006
* Tau Beta Pi, Eta Kappa Nu, Phi Eta Sigma, Phi Beta Kappa and Golden Key honor societies
Publications
* M. Cianchetti, D. Albonesi, “A Low Latency, High Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors,” ACM Journal on Emerging Technologies in Computing Systems (JETC '11), Special issue on Nanophotonic Communication Technology Integration, Jan. 2011.
* M. Cianchetti, N. Sherwood, C. Batten, “Impl...
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