SUMMARY
Expert in the analysis and design of PLL RF synthesizers including system analysis, phase noise analysis, fractional N, feedback loop dynamics and detailed circuit design. Familiar with all aspects of analog, RF, and high-speed digital circuit design. Involved in system design, detailed circuit design, bread boarding, testing, and working with PC layout department, mechanical design and test engineering, solving production problems, interfacing with customers, and writing manuals and test procedures.
Skilled in the use of all modern RF/Analog test equipment including network, spectrum, and modulation/vector analyzers, and phase noise measurements. Proficient in the use of CAE programs including, ADS, SPICE, mathematical software (Mathcad, Matlab).
Designed circuits from DC to over 10 GHz using mixers (active and passive), RF and operational amplifiers, filters (active and passive), VCO’s, D to A and A to D converters, crystal oscillators, microstrip/stripline structures and high-speeddigital circuits.
EDUCATION
BS Engineering: University of Michigan
MS Electrical Engineering: Stanford University
CURRENT PROFESSIONAL EXPERIENCE
Agilent Technologies, Santa Rosa, CA and Everett, WA
2000-2013
Manufacturer of high performance test and measurement equipment for the electronics industry
Expert Level Engineer, 2000-2009
Master Level Engineer 2009-2013
Member of Synthesis Center of Technology group to pursue innovative methods and future technology for frequency synthesis. Successful implementation of many high performance synthesizers for sources, network analyzers and
spectrum analyzers. Consulting and mentoring to other groups regarding frequency synthesis and PLL design. Worked with internal FAB and external vendors to develop specialized components. Taught PLL design classes at various
Agilent sites (Penang, Malaysia; Chengdu, China and Santa Rosa CA). Mentored engineers in PLL, RF, analog design, and hardware de-bugging.
Project Responsibilities
* Architecture
* Block diagram
* Analysis and mathematical modeling
* Proof of concept bread boarding and producing reference design circuit boards
* Assisting the design engineers in the detailed circuit design
* Solving production problems
* Presenting papers at internal technical conferences and writing articles for trade publications
Major Projects Completed
* Major contributor in the design of Agilent’s 3rd generation fractional N PLL system. Built and evaluated complete “reference design” PCB for both VCO and YIG oscillators and achieved better than -75 dBc near integer boundary spurs.
This design is used in a large number of Agilent sources, network analyzers and spectrum analyzers.
* Improved close-in noise for older generation microwave signal source.
* Designed YIG based microwave signal source based on a new triple loop design
* Low noise 4.8 GHz oscillator using carrier cancelling delay line delay line discriminator technique.
* Low noise clock source used in BERT’s and other products.
* Latest generation of RF signal sources using a lower cost version of the triple loop design
* Low power LO for hand-held network/spectrum analyzer.
* Low noise, low cost clock oscillators for scopes and other applications
* Ultra-low noise clock source for next generation microwave signal source.
PREVIOUS PROCESSIONAL EXPERIENCE
Gigatronics, San Ramon, CA
1993-2000
Manufacturer of microwave test equipment
Senior RF Engineer (FTE, contract)
* Responsible for sustaining engineering...
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