Objective
My objective is to find a company that will utilize my hardware design skills/experience and provide me with a challenge beyond my current expertise level.
Employment
2013-014(Contract)
Logicircuit
Alpharetta, GA
FPGA Verification Engineer
* Was responsible with the verification of Xilinx IP for DO-254 compliance. The Xilinx IP being verified was AXI-based for use within Xilinx Embedded Design Kit (EDK). Followed the DO-254 hardware verification process for IP verification that included creating IP design requirements, creating a test plan to verify those requirements, designing VHDL/Verilog models/testbenches for simulation test environment and creating test cases that followed/verified the created test plan. The Xilinx IP verification for DO-254 compliance was done in both simulation and lab environments.
2012-2012(Contract)
Orbital Sciences
Dulles, VA
FPGA Design Engineer
* Was responsible for designing and implementing Actel FPGAs, in VHDL, for space satellite applications. Worked mainly on the next generation Command and Data Handling (C&DH) satellite subsystem. Some of the functions that were implemented were a proprietary serial communications bus for inter-FPGA communication, A/D data control/collection, data packetizing and memory interfacing. Actel Designer 9.1 was used for Actel FPGA implementation, Aldec Active-HDL for VHDL design/verification and Synopsys Synplify Pro for synthesis.
2011-2011(Contract) SEAKR
Centennial, CO
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL/Verilog, for aerospace data storage and processing solutions as follows:
* Designed various functional logic blocks, in Verilog, for a solid-state recorder system. The Xilinx Virtex-5/SIRF device was used for logic implementation and built using ISE 12.3. The logic blocks were designed around a FPGA internal switch fabric that interfaced to several serial-RapidIO (SRIO) ports, SERDES control logic to/from other FPGA devices, FPGA internal control/status and built-in self-test (BIST). The system dataflow was controlled using router logic within the FPGA that allowed data storage to/from various memory storage cards. A SystemVerilog testbench was used to simulate and verify the FPGA and system dataflow using QuestaSim.
* Worked on a communications satellite processing subsystem. Designed and implemented a Xilinx Virtex-6 device for a test card that would be used for various dataflow test methods. The FPGA was designed using EDK 13.1 and contained a mixture of EDK library logic and commercial/custom IP. The various data interfaces implemented for dataflow included PCIe, DDR3, I2C, GPIO, SERDES and Ethernet. The main logic was designed using Verilog, although the design did have a mixture of VHDL/Verilog. Also designed a custom DDR interface controller for the communications processing system using Verilog and was to be used in a Virtex-5/SIRF device.
2008-2010(Contract)
Valley Technologies
State College, PA
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL, for a 8-channel optical multi-gigabit data accumulator/mapping card. There were 2 Xilinx Virtex-II Pro FPGAs used for the multiplexer/de-multiplexer data transfer architecture. The multiplexer FPGA multiplexes up to eight serial streams, from the 8-channel RocketIO interface, of various types/rates into a single composite bit stream of approximately 9.42 Gbps. The de-multiplexer FPGA reverses the multiplexer FPGA mapping by de-multiplexing a single composite stream into up to eight serial streams. The de-multiplexer FPGA also had two independent modules of 2GB DDR2 SDRAM for recording received data traffic. Both FPGAs interfaced with a PowerQUICC II for processor applications. The Xilinx Virtex-5 FXT device was later used to upgrade both FPGAs performance/flexibility. Xilinx ISE 9.2/11.5 was used for FPGA implementation, ModelsimPE for verification and XST for synthesis.
2007-2007(Contract)
Gerber Scientific Products
Hartford, CT
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL, for an industrial inkjet printer product. Several Xilinx Spartan-3E FPGAs were used to implement print data control logic along with printer electrical control interfaces. The print data control logic functional blocks included a source-synchronous serial I/F, PowerQUICC III Microprocessor (PCI, Local Bus) I/F, Atmel USB AVR Microcontroller (8051) I/F and pixel data formatting/flow-control The main printer electrical control functions implemented were motor control (Stepper, Servo, DC), Delta-Sigma ADC/DAC for printhead heater/power control and internal timer/interrupt controllers. Xilinx ISE 8.1 was used for FPGA implementation, ModelsimPE for verification and XST for synthesis.
2006-2006(Contract)
Qualcomm
San Diego, CA
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL/Verilog, for use on a CDMA-functional development platform. Work involved parsing ASIC Verilog code across multiple Xilinx Virtex-4 FPGAs, which allowed for chip verification and early software development. The FPGA code development was a mixture of VHDL/Verilog wrappers and included chip-level functional parsing, clock synthesis/distribution, reset control and high-speed inter-FPGA communication modules. Xilinx ISE 8.1, along with Chipscope Pro 8.1, was used for FPGA implementation/verification and Synplify Pro for synthesis.
2006-2006(Contract)
Navini Networks
Dallas, TX
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL, for use within WiMAX products. These products are part of the next generation in wireless broadband. The functions implemented were based on switch-fabric architecture between the FPGA and one or several TI OMAP5912 application processors within WiMAX base stations and PCMCIA-based modem cards. Xilinx ISE 8.1 was used for the high-density Virtex-4 and Spartan-3E FPGA implementation and ModelsimPE was used for design verification.
2005-2005(Contract)
Nova Engineering
Cincinnati, OH
FPGA Design Engineer
* Was responsible for designing and implementing FPGAs, in VHDL, for use within telemetry systems hardware. Some of the functions implemented, including DSP-based functions, were frequency tracking, resampler, timing adjuster, correlators, PCM/FM trellis along with various filters like moving average and FIR. Xilinx ISE 7.1 was used for the high-density Virtex-II and Spartan-3 FPGA implementation and ModelsimPE was used for design verification.
2004-2005
Artesyn Technologies
Madison, WI
Hardware Design...
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