Key Technical Strengths
* Transistor level circuit design.
* Implemented OTA, Bandgap ref. gen., LDO, VCO, PLL.
* Systemverilog, Verilog, Verilog AMS programming.
* SPICE and Cadence ADE integrated circuit modeling.
* FPGA(D-Verilog) RTL design.
* Verilog-AMS based ADC/DAC modeling.
* Python, C/C++ programming
* knowledge in transmission line effects, S-parameters, Smith chart theory.
* Linux shell scripting.
* Matlab/Simulink based modeling.
Education
* Utah State University, GPA: 3.59/4.00
Jan. 2010 – May 2013
Master of Science in Electrical Engineering;
– Key Courses: Real Time Processors, Applied CMOS, Digital System Design, Analog VLSI, Optics, Electromagnetics, Computational Electromagnetics, Mixed Signal Design, Micro-electronics, Thesis.
* University of Mumbai
Jun 2005 – May 2009
Bachelor of Engineering in Electronics and Telecommunications
Project Experience
• Low Drop-out Regulator in 0.6 um technology in Cadence Virtuoso:
– Target specifications to design the LDO: V in(min−max) = 3.5V − 5V , V out = 3.3V , IQ ≤ 30mA, VDO ≤ 200mV .
– Implemented PMOS power element, reference generator and, 2 stage feedback current mirror amplifier with 75 db gain and unity gain freq. at 400 MHz.
– Post extracted layout simulations resulted in VDO of 114mV @ 3.638mA, IQ of 17mA, line regulation of 138mV /V and, load regulation of 18mV /mA.
• Pipeline ADC model using Verilog AMS:
– Aim: To implement a pipeline ADC behavioral model to characterize finite gain OP-AMP errors.
– A behavioral model of generic 2 bit pipeline ADC implemented using ideal circuit device level functional blocks.
– Finite gain OP-AMPs implemented in each stage of the ADC resulted as added noise in the residue voltage of each pipeline stage.
• Real Time Processors Lab:
– Implemented digital FIR, IIR, adaptive filters, FFT analysis on TMS320C67xx DSP chip .
– Celoxica RC200 FPGA based edge detector implemented using Sobel filter.
• Implemented a 8-bit Serial Parallel Multiplier circuit (schematic and Layout) using Tanner tools with an objective to design a CMOS digital circuit requiring more than 4000 transistors.
• A 16 x 16 systolic array multiplier coded in Verilog in implemented on a ...
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