SUMMARY
Accomplished and results-oriented engineer with extensive experience in quality assurance, manufacturing, process integration and research & development. Proficient in design of experiments (DOE), LEAN concepts, 6-sigma statistical and troubleshooting methods, process control plans and associated SPC. Highly skilled in intellectual property development as evident by my 20+ patents. Competent ramp readiness engineer responsible for: FMEA development and sustaining, control plans, and initial defect density, root cause responsibility and failure analysis. Evaluated existing processes and implemented improvements to optimize performance, reduce variance and expenses. Successfully led 2 process integration engineers and 5 unit process engineers in development of Thin Film Resistor (TFR)-enhanced processes with margins in excess of $500,000,000 annually. Recently completed LEAN 6-Sigma and 6-Sigma Black Belt class at Villanova University.
EXPERIENCE
TEXAS INSTRUMENTS, Tucson, Arizona
Process Integration/Development Engineer 2008-2012
Well reputed subject matter expert for extending processes and products capability that further differentiated mixed signal and analog products. Specialized in Thin Film components, their integration and reduction of their parametric variance. Directed a materials development team that used internal, academic and vendor resources. Research focused on higher resistivity alloys with near zero temperature coefficients.
• Modified the existing metal resistor alloy to reduce Temperature Coefficient of Resistance (TCR) by 90%.
• Led width reduction team of 4 engineers that achieved a 79% reduction in minimum line geometry.
• Reduced die size and parasitic capacitance by enabling resistor integration over anything.
• Identified root cause and fixed incomplete etch issue associated process integration and tool configuration.
• Lead failure analysis to find root cause for 1/f noise issue. Applied Design of Experiments (DOE) methods to eliminate 1/f noise issue due to interface anomalies.
• Successfully transferred components for a high-volume, mixed-signal process to Texas Instruments fab in Japan.
• Trained numerous process, integration and product engineers in receiving fab with process-related primers concerning unique aspects of components and process sensitivities. Trained test engineering on characterization methodologies.
• Led and worked closely with receiving fab on DOE definition, execution and analysis, which resulted in centered component parametric and Cpk exceeding that of sending fab.
• Produced, over 300 higher resistivity alloys, using co-deposition in PVD and PLD systems.
• Optimized laser trim structures on to improve electrical response and reduce collateral damage.
Process Ramp Readiness Engineer 2003-2008
Ensured optimization for process and component quality from conception through the first 6 months of ramp. Developed component matrix, control plans, component FMEA, process FMEA, monitored defect density and drove root cause investigations and corrective actions. Collected & archived Lessons Learned and assured all deliverables met deadlines.
• Directed component layout, electrical test limits, and data analysis for integrated yield monitoring (IYM) to establish component defect densities. Used methods to identify and resolve particle, layout, process and integration issues.
• Responsible for presenting quarterly updates for all deliverables, as well as project deliverable scorecard.
• Defined end-of-line e-test structures and in-line process monitoring structures.
• Led short-term team to attack yield crash at different facility. Increasing end of line e-test yield from near zero to >96% and probe yield to >85%. Found and resolved 24 test and process issues using 6-sigma methods over 4-month period.
• Problems fixed included Schottky diode barrier height and ideality parametric shift, BEOL charge issue that creating strong parasitic PMOS device, Probe contact resistance issue, planarization , Resist coat-Stepper-developer errors, PVD shield configuration optimization, via and Contact Rc issues.
• Actions resulted in process that delivered more than $30,000,000 in revenue per year.
TFR Process Integration Engineer 2000-2003
Thin Film Resistor (TFR) component champion. Directed all corporate-wide process development, troubleshooting and process definition.
• Led eight-person team and resolved six-month old critical dimension (CD) control issue within three weeks. Followed-up with optimized process to improve matching coefficient and lower TCR.
• Developed world leading TFR process (HPA07) by applying lessons learned to overall process integration. Submitted nine patent proposals and earned eight patents during development and ramp of process. Achieved industry’s best resistance densities, enabling z-integration, lowest matching coefficient, and near zero Temperature Coefficient of Resistance.
• Integrated TFR over anything at 0.7um and larger.
• Reduced the effect of current-induced self-heating by 70% through creative use of device topology.
• Developed laser trim structure compatible with large dielectric variance induced by CMP that allowed successful trimming.
• Developed method to improve material nucleation on dielectric substrate which reduced matching coefficient by 20%.
• Designed a unique termination method that reduced parasitic contact resistance variance in TFR.
• Achieved 16- and 18-bit DAC products on process without laser trimming saving $1000’s/wafer.
ADDITIONAL EXPERIENCE
BURR-BROWN RESEARCH CORP., Tucson, Arizona, BEOL Process Integration, 1995-2000. Responsible for integration from contact formation to end of li...
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