OBJECTIVE: Seeking a challenging position in ASIC Design where I can effectively utilize my skills and hands-on learning to develop new systems.
EDUCATION:
Master of Science in Electrical Engineering (Concentration: VLSI) GPA: 3.70 / 4.0
State University of New York at Buffalo, Buffalo, New York June 2013
Bachelors in Electrical and Electronics Engineering GPA: 7.24 / 10.0
Birla Institute of Technology Mesra, Jharkhand, India January 2012
ACADEMIC COURSEWORK: Computer Architecture, Analog Circuits, Introduction to VLSI Electronics (Digital Electronics), Microelectronic Device Fabrication, RF & Microwave Circuits, Digital Signal Processing, Sequences & Codes in DSP, Wireless Sensor Networks, MIMO Wireless Communications, Principles of Information Theory & Coding
TECHNICAL SKILLS:
Programming Languages : C, C++, Verilog HDL
Scripting Languages : Awk, Tcl, Perl, Bash
Design Software : Cadence Virtuoso, SPICE, Ansoft HFSS, Xilinx ISE, MATLAB
Network Protocols : TCP / IP
Application Software : MS Office, Open Office
Operating Systems : Windows, Linux, Open Solaris
RELATED EXPERIENCE:
Intern, High Performance VLSI Systems & Architecture Lab, SUNY Buffalo October 2013 - Present
- Currently working on Design and Verification of a FIFO using Verilog HDL.
ACADEMIC PROJECTS:
Implementation of Two Player Guessing Game using Verilog HDL Spring 2013
- Project includes programming the design, creation of a slow clock sub routine (50 MHz to 25 KHz), floor planning, port assignment and creation of an executable bit file that can be loaded into the BASYS2 FPGA (Xilinx Spartan3E) Board during simulation.
- Used Xilinx ISE Suite for design and synthesis, Xilinx Plan Ahead Software for floor planning, and Xilinx Adept Software for creation of an executable bit file.
Design and verification of a Low-Power SRAM Memory using 8T SRAM Cells Fall 2012
- Designed the principal circuits and their components such as 8 Transistor SRAM Cell (Body Biasing Technique), Decoder, Pre-Charge, Data Write and Sense Amplifier.
- Prepared the schematics and layouts of the SRAM Memory using Cadence Virtuoso Schematic and Layout Editors, carried out Padframe Integration, Design Rule Check, RC Parasitic Extraction and LVS Check.
- Simulated the design in Cadence Virtuoso environment for various constraints such as functional accuracy, minimal on-chip area and reduced power consumption in comparison to a conventional memory.
Design of a Selectable Gain Audio Amplifier to drive a 50 Ohm Load Fall 2012
- Project included the design of a PMOS transistor and Cascoded Current Mirror at the Bias Stage, Differential Amplifiers with NMOS Transistor Load (for 10dB Gain) and PMOS Current Mirror Load (for 40dB Gain) at the Input Stage and NMOS Common Drain Configuration for the Output Stage.
- Designed a Miller Capacitance to achieve frequency response in the Audio (20Hz – 20 KHz) Range.
- Prepared the schematics and layouts of the amplifier using Cadence Virtuoso Schematic and Layout Editors, carried out Padframe Integration, Design Rule Check, RC Parasitic Extraction and LVS Check.
- Simulated the design in Cadence Virtuoso environment to meet the constraints of CMRR of 120dB, Total Harmonic Distortion lesser than 5%, Output Voltage centered at 0V.
Design of a 10dB Parallel Line Coupler to meet given specifications Spring 2012
- Determined the value of characteristic impedance via simulation to achieve Directivity of 12.5dB, Coupling Factor of 9.5dB and Insert...
Login or Register to view the full resume.
