Education
M.S., Electrical Engineering, West Virginia University, 1997
B.S., Electrical Engineering, West Virginia University, 1992
B.S., Computer Engineering, West Virginia University, 1992
Clearance
Secret (2007-Present)
Top Secret (1996 – 1997)
Secret (1993 - 1995)
Experience Overview
• Experience as a Systems Integrated Product Team Lead for the Brigade Combat Team Modernization Program and Systems Deputy IPT Lead for the Common Range Integrated Instrumentation System Program
• Experience and specialization in high speed digital design, including work with Cryptographic and TEMPEST related designs
• Experience in multiple PCB designs from proof of concept to manufacturing and production. The designs consisted of the following: Altera and Xilinx FPGAs, Freescale P2020 Processor, Intel’s IXP1200 Network Processor, Pentium Processor, 486 microprocessor, and 386EX microprocessor; Blackfin, TMS320LBC56, TMS320LC542, and AD2185 DSPs; AD1847 CODECs, Flash Memory, Synchronous/Asynchronous SRAM, DDR2/3 SDRAM, AD9852 DDS, ADCs and DACs, and RTCs.
• Experience includes the planning and scheduling of resources, board design, signal integrity analysis, timing analysis, board layout, software development, hardware and software interfacing, and programming, debugging and troubleshooting at the board level, the functional level, and the system level. Experience also includes overseeing the hardware/software development of these boards and interfacing with other departments, companies, contractors, and manufacturers.
• Experience in FPGA designs with Serial RapidIO, PCI, and local bus interfaces, DDR2 SDRAM controllers, multiple time domains, and Multi-Gigabit Transceivers.
• Experience in various processor interfaces and communication protocols including ATM Blade designs, Ethernet, PCI, PCI Express, USB, SPI, I2C, RS485, and RS232.
• Experience in developing In-Circuit, Functional, and System Level Test Plans
• Experience in designing products to be compliant with FCC Part 68, FCC Part 15, and UL 1459 regulations. This includes a large design emphasis on noise emission, suppression, and immunity, as well as safety issues including over voltage protection, isolation, and ESD protection. Boards were also designed to be RoHS compliant.
• Experience in Real Time Operating Systems
• Experience in programming includes the development of an operating system, an interpreter, JTAG and Flash/Xmodem programming and debug tools, BIOS level code, Board Support Packages, designs in various assembly languages, designs utilizing C, ADA and Motif, and XMIDAS scripts.
Employment History
December, 2008 – Present: Rockwell Collins, Senior Systems Engineer (IV)
• Commercial Systems ASIC/FPGA Engineering
Responsible for requirements development for Serial RapidIO (sRIO)
Responsible for developing sRIO test environment (2 lanes @ 2.5Gbps) and FPGA code for Xilinx Artix 7 FPGA and then integrating with hardware and software.
• Commercial Systems Onboard Maintenance Systems (OMS) – Project Engineer
Responsible for managing schedule, budget, resources, and bids for Onboard Maintenance System for Fusion Programs and Legacy Programs which utilized the Maintenance Diagnostic Computer (MDC) and the Data Base Unit (DBU).
Responsible for OMS software integration for the Embedded Display System (EDS)
• Govt Systems Common Range Integrated Instrumentation System – Systems Deputy IPT Lead
Responsible for Systems Change Control Board and Program Change Management
Responsible for managing conflict resolution on technical issues across IPTs
Served as Document Lead for L3 SSS Requirements and the CRIIS Master ICD / IDD
Served as Lead for Alt ECU Design Approach Review and Lead for CR Tiger Team
• Govt Systems Brigade Combat Team Modernization – Systems and Sustainment IPT Lead
Responsible for oversight of a Systems Engineering Team, a Reliability, Accessibility, Maintainability and Testability (RAM-T) Team, and an Integrated Logistic Support (ILS) Team.
Responsible for oversight and development of system requirements and system design for an Armed Reconnaissance Vehicle (ARV) and a Large Network Processor (LNPv2) in conjunction with General Dynamics. This included ensuring that the overall system was compliant to the requirements and guaranteeing consistency across platforms.
Responsible for oversight of three Cost Account Managers (CAMs), Earned Value (EV) Metrics, Variance Reports, Staffing Profiles, Schedule, Budget, Bids and Proposals.
Leadership responsibilities included team motivation, mediation and conflict resolution, coordination of tasks and resources, interfacing with customers and vendors, mentoring junior engineers and stressing the importance of quality workmanship, within schedule and within budget.
• Govt Systems Common End Cryptographic Unit – Lead Hardware Engineer
Responsible for CRIIS Phase 1 Hardware Requirement Specification and Hardware Design Document. This included preliminary design for Electrical, Firmware, and Mechanical Configuration Items. Design included a Cryptographic Engine, Spartan 6 FPGAs, Freescale P2020 microprocessor, 800MHz DDR3 memory and Gigabit Ethernet.
Assisted in Bid and Proposal for Phase 2
• Govt Systems Common Cryptographic Sub-System
Responsible for detailed signal integrity and timing analysis using Timing Designer and HyperLynx toolsets for interfaces up to 100MHz.
Responsible for Thermal Analysis
• Govt Systems and Commercial Systems Bids and Proposals
November, 2006 –December, 2008: DRS Intelligence and Avionic Solutions, Senior Hardware Design Engineer (IV)
• PCI Express
Responsible for firmware development for the Xilinx Virtex-5 LX50T FPGA consisting of a DDR2 SDRAM controller and a 128 channel DMA arbiter.
Experienced in detailed timing analysis and timing constraints with memory speeds up to 533MHz with clock domains up to 266 MHz.
• Coherent Recorder
Responsible for firmware development for the Altera Stratix II GX FPGA consisting of DDR2 SDRAM controller, DDS interface, TOY, Playback and Record. This was a team effort and the project consisted of a Receiver Interface chassis (4 Channel Cards, Control Board, and an SBC) and a Recorder Interface Chassis (4 Channel Cards, Control Board, and an SBC).
Used XMIDAS scripts for low-level software/hardware integration and debugging
• JTT-IBX : Joint Tactical Terminal – Intelligence Broadcast Transceiver
Responsible for the design and testing of the JTT Front Panel
Responsible for FPGA development of an Elapsed Time Indicator
Responsible for various hardware integration related issues
Responsible for building and testing third party FPGA firmware
• AHHS : Altitude Hold and Hover Stabilization
Responsible for Glare Shield Indicator specifications and supplier interface...
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