OBJECTIVE: to work as part of a design team as a VLSI Design, Verification, or DFT Engineer in a progressive company that values and encourages teamwork.
SKILLS
Mentor Scan tools, Verilog, VHDL, Perl, debugging, long term planning.
WORK EXPERIENCE
16 years as a Design Engineer consisting of:
14 years as a DFT/Verification Engineer(roughly 9 in DFT and 5 in Verification)
2 years as a Synthesis and Custom Circuit Design Engineer
Oracle (formerly part of Sun Microsystems acquired by Oracle)
Jan. 06 to Present DFT and Verification Engineer
Owned Stuckat and Transition Test Pattern generation for a few generation of Enterprise CPU's and one big ASIC chip. Was a key contributor for recent generations of CPU's especially in Transition Test. Was an MBIST verification engineer for a year or two. Was an MBIST designer for a project. Wrote verification tests for several DFT related CPU features. Have experience in DFT in all stages of chip development from start to finish from working closely with the design team to make the chip DFT friendly through to making sure patterns work properly and are screening the parts well in post silicon phase. Owned and verified DFT scan logic guidelines.
Contract DFT Engineer for INGOT,ELA,VINCHIP working at PMC-Sierra, ATI and TI
OCT. 04 to Dec.05 Contract DFT Engineer
Helped implement DFT features and reach high fault coverage on highly modularized logic blocks for an ASIC. Drove path delay fault testing on a large chip. Designed an extended instruction JTAG block and verified it using Specman. Drove transition fault testing on a large SOC sub-block project. Inserted Scan with Mentor tools.
INTEL
July 1999 to June 2004 Microprocessor Design Engineer
Intel Project and task breakdown:
Dec 02 to June 04 Synthesis and Circuit Design on Yonah CPU in Centrino CPU Family
Jan. 01 to Nov 02 Design For Test on Madison CPU of the Itanium CPU Family
July 99 to Dec 00 Fault grading of Merced CPU of the Itanium CPU Family
Intel Highlights:
Was a main contributor in the development and successful deployment of high scan coverage from ATPG tools for the Madison CPU. Led a small group of junior engineers. Proactively developed innovative techniques which proved highly successful through long term planning. For example, when previous projects test coverage failed in many respects(not my project) was able to root cause the problem to inaccurate gate level model of the design and proactively make sure the new projects models were correct from basic building blocks all the way up to logically consistent full chip tapeout models. Modeled complex Fastscan(Verilog) gate level models including dynamic circuitry.
Various other Jobs:
Jan. 96 to June 99 Advanced Technical Support
Creative Labs Inc., Stillwater, OK
Responsible for technical support for Crea...
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