OBJECTIVE
Proficient, Passionate and over 1 year Experienced Engineer eager to contribute technical expertise as well as strong educational and engineering skills in a challenging ASIC, FPGA, and Hardware Design assignment actively supporting an organization in maximizing performance.
EDUCATIONAL AND CAREER SUMMARY
• M.S. Electrical Engineer graduated from Florida International University with 3.8 GPA out of 4.
• B.S. Electrical Engineer graduated from SCET University, Gujarat with 3.89 GPA out of 4.
• More than 1 year of combined relevant ASIC, FPGA, Hardware Design, Testing, Circuit Design experience.
• Proficient in ASIC/FPGA/Hardware design, testing, validation, verification and integration.
• Knowledgeable in physical design for digital and analog/mixed signal semiconductors.
• Knowledgeable in Hardware, Networks, Verilog Programming, RTL and VHDL Coding, C Programming, Perl Scripting, Xilinx, AC-DC Controller, Micro-controller, Microprocessors.
• Strong focus on exceptional customer service/support, quality and meeting organizational objectives.
• Contributor in increasing proficiency in challenging environment.
• Well-organized, multi-tasker and team player with strong detail orientation.
• Permanent Resident of US (GC Holder)
EXPERIENCE
Meena Infosystems Private Limited (India) DEC 2009 – JUN 2011
Entry Level Hardware Engineer/Electrical Engineer
Meena Infosystems Private Limited is SOC design Services Company offering design consulting and services in digital, analog/mixed signal design and software development.
• One of the big parts of the engineering job is to design specs and building complete products, with ASIC design services that include RTL design, design verification and physical design for digital and analog/mixed signal semiconductors.
• Recruited right after the graduation in 2010 to support senior engineers in developing new products
• Participate in designing, analyzing and implementing digital processing.
• Participate in designing board layout, routing, VHDL simulation and analysis. Also participated in breadboard testing and troubleshooting.
• Tasked under senior engineer supervision to oversee ASIC architecture, implementation, testing and verification.
• Tasked to perform verification and validations using Verilog programming language.
• Above project included RTL coding, simulation, synthesis and formal design verification.
• Participated in supporting FPGA design including verification and synthesis.
• Also tasked to redesign new AC-DC controller to meet company specification.
• Closely worked with Senior Engineers, Project Managers and Leaders in above tasks.
• Worked with Project Manager and Senior Engineers to gather requirements of the client and deliver project on time.
EDUCATION
FLORIDA INTERNATIONAL UNIVERSITY (FIU) MIAMI, FL
Masters of Engineering (M.S) in Electrical Engineering, May 2013 (GPA – 3.8)
VEER NARMAD SOUTH GUJARAT UNIVERSITY SURAT, INDIA
Bachelors of Engineering in Electronics and Telecommunication Engineering, June 2010 (GPA – 3.89)
PROJECTS
IMPLEMENTATION OF STREAMING CAMERA USING FPGA AND CMOS IMAGE SENSOR APR 2013
• The goal of this project is to construct a small camera system capable of streaming live video images from a CMOS image sensor to a PC
• The program loaded on Xilinx 3S500E FPGA using Verilog has three main task: to control the CMOS image sensor, to read and store pixel data from the OV7670 CMOS image sensor and to stream the pixel data to PC through the parallel port of FPGA via VGA interface
• The software is divided into several modules like Camera modules, controller, capture logic, ram and VGA generator each performing a specific function
SQUARE WAVE GENERATOR USING MENTOR GRAPHICS NOV 2012
• Ring Oscillator is implemented in Mentor Graphics Pyxis schematic “A Design Environment”
• A ring oscillator is a device composed of odd number of NOT gates, an inverting amplifier, whose output oscillate between two voltage level
• Analysis shows that wave generated from the initial noise may not be square but as it grows, it will become square as the amplifier reaches its output limits
• Simulation is run using Eldo simulator
BENCHMARK PROFILING AND PROCESSOR ARCHITECTURE AUG 2012
• Simple Scalar simulator is used to profile the execution of several benchmark programs
• Analyzing the performance of different computer systems based on these benchmark programs, and to examine the roles of the compiler.
INSTRUCTION LEVEL PARALLELISM SIMULATION SEP 2012
• Simple Scalar is used to study the pipeline performance and related techniques for instruction level parallel (ILP) exploitation.
REACTIVE NAVIGATION IN INDOOR ENVIRONMENT APR 2010
• Describe motion of robot from source to destination by avoiding obstacles
• Uses Fuzzy Logic and Sensors to create its path
CALCULATOR USING 8051 MICORCONTROLLER DEC 2009
• Interface of push button switch and LCD with microcontroller
• Operation such as Addition, Subtraction...
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